🧬 MutaMac: Gate-Level Hardware DNA Mutation Scanner

A high-performance, edge-triggered hardware accelerator designed from scratch using fundamental logic gates to perform real-time, comparative genetic sequencing. By eliminating software abstraction layers, compilation runtimes, and high-level arithmetic units, MutaMac streams raw genomic text files directly through an array of synchronized hardware components to detect, count, and isolate structural nucleotide variations (mutations).

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🎮 Project Showcase & Video Trailer

Video.Project.1.mp4

Hardware Showcase MutaMac Development Hyper-Lapse & Simulation Watch the entire development workflow compressed into a high-octane architectural trailer. From raw NAND/NOR latches to building fully synchronous multi-bit carry chains and deploying a complete dual-ROM genetic comparative system capable of processing stream buffers at runtime.

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📝 Introduction

Modern bioinformatics heavily relies on software alignment algorithms (like Smith-Waterman or Needleman-Wunsch) executing on top of generalized CPU architectures. While highly flexible, these abstractions introduce massive processing overheads via instruction fetching, caching delays, and branch mispredictions.

MutaMac explores the alternative: Hardware-Native Genomic Processing.

Designed to sit at the exact intersection of Digital Logic Design and Bioinformatics Engineering, MutaMac implements a specialized Application-Specific Integrated Circuit (ASIC) architecture optimized purely for stream-based variant scanning. By implementing state machines, parallel comparators, and carry chains wire-by-wire out of fundamental logic gates, the platform achieves execution times bounded purely by the gate propagation delay of the physical hardware clock cycles.

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🚀 Key Features

• Zero-Abstraction Data Path: Built strictly out of primitive discrete components (NAND, NOR, XOR, AND, NOT). No high-level hardware description language compilers or pre-packaged black boxes.
• Direct ASCII Character Ingestion: Standard 8-bit ASCII characters (A, C, G, T) are loaded, memory-mapped, and evaluated natively as raw string streams, bypassing the need for an intermediate decimal-encoding layer.
• Cycle-Accurate Synchronous Design: Every execution phase is fully synchronized with a central Master Clock distribution line, guaranteeing absolute immunity against dangerous timing race conditions or propagation delay "glitch sparks."
• Persistent Boundary Protection: Employs an integrated 8-input boundary detection matrix that permanently freezes execution cycles precisely at sequence index 255 ($0xFF$), ensuring deterministic termination without logic oscillation or state crashes.
• Real-Time Visual Telemetry: Drives dual hexadecimal 7-segment hardware display boards to output accurate, updated variation counts instantly during runtime simulation.

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🎯 Architecture Overview & Flow

MutaMac is implemented inside the Digital logic simulation framework. It operates by fetching parallel byte streams from twin non-volatile memories (ROM arrays holding Reference Sequence A and Variant Sequence B) encoded as literal standard 8-bit ASCII characters.

A master control unit manages the clock distribution loop, driving an indexing address counter through $256$ continuous memory addresses. As the memory bytes dump simultaneously into a custom parallel bitwise comparison array, structural differences drive a specialized synchronous sampling filter. The final mutation tally is automatically decoded and presented on a clean dual-hexadecimal visual telemetry board, halting execution precisely at address boundary 255 ($0xFF$) to prevent overflow.

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📂 Repository Directory Tree

The project file layout is meticulously partitioned across thematic structural directories to keep subcircuit dependencies modular and cleanly isolated:

MutaMac/
├── main.dig                      # Top-level schematic assembly and interconnect matrix
├── README.md                     # Comprehensive technical documentation
├── Arithmetic/
│   └── fullAdder.dig             # Gate-level 1-bit full adder primitive
├── Control/
│   ├── controlUnit.dig           # Bi-stable SR latch clock management block
│   └── nuccDiff.dig              # 8-bit parallel bitwise XOR matching array
├── Storage/
│   ├── counter_8bit.dig          # 8-bit synchronous look-ahead cascade counter
│   ├── d_flip_flop.dig           # Edge-triggered master-slave D-FF with synchronous enable
│   └── d_latch.dig               # Gated NAND-logic transparent D-latch with active-low clear
└── data/
    ├── seqA.txt                  # Reference sequence data file (8-bit ASCII space-separated)
    └── seqB.txt                  # Target sequence data file to test for mutations

🛠️ Complete Component Breakdown & Technical Specifications

1. Main System Core (main.dig)

The top-level coordination fabric. It routes power, links the synchronous buses, and hooks up user inputs (STA for Start, RESET, and the physical hardware MASTER CLK source).

• Logic Loop Fix: To eliminate simulator crashing via infinite feedback loops, the system implements a strict separation between tracking and clearing. An 8-input structural AND gate samples the primary address line. The instant it evaluates to 255 (11111111), it issues a persistent stop signal directly to the STO pin of the control latch, locking the clock distribution network in a static 0 state without wiping out memory indices or counts.
• Glitch Filtration: To prevent propagation delay sparks (ripple artifacts) from registering as fake mutations, the raw comparison stream is routed through an isolated tracking D Flip-Flop acting as a synchronous window filter before entering the accumulation counter.

2. Control Latch Engine (Control/controlUnit.dig)

The central execution brain of MutaMac is built out of a cross-coupled, bi-stable NOR-gate SR Latch configuration.

• Operational Theory: Pressing the STA button inputs a high pulse to the top gate, setting the RUN line to high. This opens the system's central AND gate, allowing the MASTER CLK signal to feed into the computational components.
• Automatic Intercept: When the system reaches the terminal sequence boundary, or if a manual STO pulse is generated, the bottom NOR gate flips the internal state instantly, pulling RUN to ground and freezing all operations in place until a manual hardware reset is triggered.

3. Bitwise Genomic Matcher Array (Control/nuccDiff.dig)

A high-throughput parallel comparison array capable of evaluating data bytes instantly at the hardware layer.

• Architecture: It accepts two independent 8-bit buses ($R_0 \dots R_7$ from the reference ROM, and $S_0 \dots S_7$ from the target sequence ROM). Eight discrete, parallel XOR gates compare the corresponding bits line-by-line.
• Reduction Layer: The outputs of all eight XOR gates pass into a massive wide-input reduction OR gate. If any single bit mismatch is encountered anywhere inside the ASCII characters, the Miss wire instantly surges to 1.

4. 8-Bit Synchronous Cascade Counter (Storage/counter_8bit.dig)

To maintain clean phase transitions and total immunity from the multi-nanosecond timing race conditions inherent in simple ripple counters, MutaMac utilizes a highly optimized Synchronous Counter with Carry-Look-Ahead Cascade Enable Gate Logic.

• Synchronous Clock Bus: Every single D Flip-Flop stage shares the exact same Master CLK signal line directly. This guarantees that all bits change states at the exact same physical instant.
• Conditional Enable Logic: Toggling behavior is governed by a cascade chain of 2-input AND gates. A given bit will only flip its value on the rising clock edge if its own local enable line is driven high. The local enable line is active if and only if the primary control line (Mis) is active AND every single preceding lower-order flip-flop currently outputs a logic 1 ($Q_n = 1$).
• Independent Local Feedback Loops: Each stage contains an independent inverter loop that feeds its own inverted output ($\bar{Q}$) cleanly back to its own input ($D$). This isolates data registers completely from neighboring interference, resulting in perfect binary mathematical addition.

5. Edge-Triggered Master-Slave Flip-Flops & Transparent Latches

The low-level state-retention foundation is built layer-by-layer up from fundamental logic primitives:

• d_latch.dig: Constructed purely out of cross-coupled NAND gates to establish a stable feedback storage loop. Includes an active-low asynchronous clear line (CLR) tied directly into the cross-coupled loops to instantly force a clean zero-state output when requested.

• d_flip_flop.dig: Combines two distinct transparent d_latch units linked together in a traditional Master-Slave configuration with an explicit inverter positioned along the CLK distribution wire. This ensures that the master stage samples data strictly during one half of the clock phase, while the slave stage latches and holds that value steady for the output during the opposite clock edge, delivering precise edge-triggered synchronization.

🏎️ Interconnect Routing & Signal Path Matrix

To replicate this architectural build exactly or trace the execution flow during testing, refer to the global system bus mapping table outlined below:

Source Component	Output Signal Node	Target Destination Block	Input Port Destination	Bus Width	Signal Purpose / Functional Description
Control Board	STA (Start Button)	Control/controlUnit	STA Pin Input	1-Bit	Initiates the bi-stable latch to start computation cycle.
Control Board	RESET (Clear Key)	Storage/counter_8bit (Both)	CLR Pin Input	1-Bit	Flushes the memory address index and mutation tally to zero.
Control/controlUnit	RUN Line State	Master Gating AND Gate	Input Port A	1-Bit	Acts as the primary power gate for the main system clock line.
Address Counter	Outputs $Q_0 \dots Q_7$	System Data Splitter	Multi-wire Bus Input	8-Bit	Provides the current execution cycle step index value.
System Data Splitter	Address Bus Array	ROM Array 1 & ROM Array 2	A (Address Port)	8-Bit	Drives parallel lookup address queries inside the data arrays.
System Data Splitter	Address Bus Array	8-Input System AND Gate	Parallel Inputs 0-7	8-Bit	Continuously evaluates the stream boundary state for the value 255.
8-Input AND Gate	Boundary Hit (1)	Control/controlUnit	STO Pin Input	1-Bit	Forces an execution freeze the microsecond the array scan completes.
Reference ROM 1	Data Output Stream	Control/nuccDiff	Inputs $R_0 \dots R_7$	8-Bit	Streams the baseline reference genome character sequence (ASCII).
Variant ROM 2	Data Output Stream	Control/nuccDiff	Inputs $S_0 \dots S_7$	8-Bit	Streams the mutated target genome character sequence (ASCII).
Control/nuccDiff	Mismatch Detected	Sampling Storage/d_flip_flop	D Data Input	1-Bit	Signals that the characters scanned at the current index are unequal.
Mutation Counter	Tally Bits $Q_0 \dots Q_7$	Telemetry Output Panel	Dual Hex 7-Seg Panel	8-Bit	Drives real-time hexadecimal counter outputs directly on screen.

💻 System Requirements

To open, run, or modify the schematics within this project, you need:

• Java Runtime Environment (JRE): Version 8 or higher.
• Digital Logic Simulator: Developed by H. Schweiger. You can download the latest open-source compilation JAR file directly from its GitHub Repository.

⚡ Setup, Installation, and Execution Instructions

1. Clone the Repository: Pull this project down onto your system locally:

   git clone [https://github.com/yourusername/MutaMac.git](https://github.com/yourusername/MutaMac.git)
   cd MutaMac

2. Load the Top-Level Core: Launch the Digital application, click on File -> Open, navigate to the root folder, and select main.dig.

3. Prepare Genomic Stream Inputs: Save your desired character patterns inside data/seqA.txt and data/seqB.txt. Ensure letters are separated by standard single spaces.

4. Run the Simulation: * Click the green Start Simulation play arrow button on the toolbar menu.

   • Press the manual canvas RESET button component to assert clean inputs across all internal state registers.
   • Click STA to launch execution. Watch the dual-hex screen update dynamically as it flags, counts, and halts natively at index 255 with absolute precision!