Issues

• fmin.d/fmax.d(subnormal, ±0.0) write back the wrong value — compare's rs1Equal ignores FloatMode: ±0 and MSB-only subnormal collide as (sign,exp,fraction) tuples (FpuCore.scala:530)

  SpinalHDL/NaxRiscv#176 · Filter by author kaci1928 opened on Oct 13, 2026

• Core stalls when data FIFO is enabled in Vivado AXI Interconnect

  SpinalHDL/NaxRiscv#171 · Filter by author littlewhi opened on Oct 7, 2026

• fcvt.d.s with a dynamic rounding mode and reserved frm is executed instead of raising illegal-instruction

  SpinalHDL/NaxRiscv#170 · Filter by author wndmll643 opened on Sep 5, 2026

• MMU page-table-walk pointers are truncated to physicalWidth with no out-of-range access-fault

  SpinalHDL/NaxRiscv#168 · Filter by author wndmll643 opened on Aug 13, 2026

• FP comparisons (feq.s/fle.s/flt.s) treat subnormal operands as equal to zero

  SpinalHDL/NaxRiscv#167 · Filter by author wndmll643 opened on Aug 4, 2026

• fcvt.d.w/fcvt.d.wu with rm=DYN and a reserved frm execute instead of raising illegal-instruction

  SpinalHDL/NaxRiscv#166 · Filter by author wndmll643 opened on Aug 2, 2026

• About simulation

  SpinalHDL/NaxRiscv#165 · Filter by author littlewhi opened on May 23, 2026
  2

• VCU118 2 GB memory or more

  SpinalHDL/NaxRiscv#163 · Filter by author XC1a opened on Mar 18, 2026
  6

• Inconsistencies Observed When Accessing Certain CSRs

  SpinalHDL/NaxRiscv#160 · Filter by author fly-1011 opened on Dec 8, 2025

• LSU issue

  SpinalHDL/NaxRiscv#147 · Filter by author bantierr opened on Oct 15, 2025
  7

• Interrupt handle problem when debug

  SpinalHDL/NaxRiscv#146 · Filter by author HaroldZ32 opened on Aug 15, 2025
  5

• Error while doing sbt "runMain naxriscv.Gen"

  SpinalHDL/NaxRiscv#140 · Filter by author Rishik-Y opened on Mar 12, 2025
  9

• CachePlugin with wayCount=1 gets eventually stuck loading the same data

  SpinalHDL/NaxRiscv#131 · Filter by author 7FM opened on Feb 4, 2025
  12

• Multicore simulation and execution

  SpinalHDL/NaxRiscv#127 · Filter by author dennisdef opened on Nov 26, 2024
  11

• about the gen.scala and ifetch

  SpinalHDL/NaxRiscv#119 · Filter by author duanjiulon opened on Jul 17, 2024
  18

• Nax not trap on store fault

  SpinalHDL/NaxRiscv#116 · Filter by author atkarim opened on Jul 16, 2024
  5

• Does NaxRiscv update mtval after trap illegal_inst?

  SpinalHDL/NaxRiscv#107 · Filter by author zhangkanqi opened on May 31, 2024
  2

• about litex and dhrystone

  SpinalHDL/NaxRiscv#96 · Filter by author duanjiulon opened on Apr 30, 2024
  41

• Error in implementation of SRAW and SRAIW instructions

  SpinalHDL/NaxRiscv#95 · Filter by author Nanotrust opened on Apr 12, 2024
  3

• Changing Naxriscv instructions - command

  SpinalHDL/NaxRiscv#92 · Filter by author mdmriscv opened on Apr 10, 2024
  1

• L1/L2 cache and integration with CPU pipeline

  SpinalHDL/NaxRiscv#91 · Filter by author SoCScholar opened on Apr 8, 2024
  2

• Read a sram that is changed by other host

  SpinalHDL/NaxRiscv#90 · Filter by author HaroldZ32 opened on Apr 8, 2024
  1

• Some guidance on better timing

  SpinalHDL/NaxRiscv#89 · Filter by author tristanitschner opened on Apr 6, 2024
  3

• riscv tests with virtual memory enabled fail

  SpinalHDL/NaxRiscv#83 · Filter by author Bill94l opened on Feb 23, 2024
  3

• how to run a nax_core with a AXI4 interface

  SpinalHDL/NaxRiscv#81 · Filter by author duanjiulon opened on Feb 23, 2024
  24