All pull requests

Pull requests

• Add SYNTHESIS and FORMAL guards also when emitting assert in sv

  #1979·mrcmry opened Oct 11, 2026Contributor·

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• Add new COLOGNE_CHIP Device type to fix automatic mem generation with yosys

  #1978·mrcmry opened Oct 11, 2026Contributor·

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• Keep AXI-Lite read responses stable under backpressure

  #1976·Arthur031221 opened Oct 3, 2026·3 of 5 tasks·

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• BUS:COM:SPI:XIP Add AXI4 32bit XIP

  #1975·briansune opened Oct 3, 2026Contributor·

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• lib: bus: WishboneSlaveFactory: Only respond to requests with CYC asserted

  #1974·saqibkh opened Oct 2, 2026·1 of 2 tasks·

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• regif: check register addresses against the bus interface size map

  #1971·xjx06127 opened Sep 29, 2026·2 tasks done·

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• Add mask support to Mem.writePort

  #1970·inochisa opened Sep 27, 2026Contributor·2 tasks·

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• Add bundle assignment completeness checker to avoid dangling signals.

  #1967·facebreeze opened Sep 21, 2026Contributor·

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• Improve error reporting context for out-of-bounds register fields

  #1962·facebreeze opened Sep 9, 2026Contributor·

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• add toInt and toBigInt helper methods to SpinalEnumElement

  #1961·facebreeze opened Sep 8, 2026Contributor·2 tasks·

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• Fix fragment locking in stream fragment arbiters

  #1955·Hiyori97 opened Aug 26, 2026·1 of 2 tasks·

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• axis: support independently sized TUSER fields

  #1954·xueweiwujxw opened Aug 26, 2026Contributor·2 tasks done·

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• LIB: MATH: fix misaligned early ready

  #1941·briansune opened Jun 26, 2026Contributor·

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• Add scala 2.12.21 and scala 2.13.18 version support

  #1938·inochisa opened Jun 18, 2026Contributor·2 tasks·

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• Video IPs

  #1937·briansune opened Jun 18, 2026Contributor·41 of 42 tasks·

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• Feature/okay spelling

  #1927·Tectu opened Jun 2, 2026Contributor·

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• fix(lib): fix premature cmd.ready assertion in UnsignedDivider

  #1917·Aqwyh123 opened May 20, 2026Contributor·2 tasks·

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• Add default for uninitialized register in jtag

  #1902·jdavidberger opened Apr 16, 2026Contributor·

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• Add Companion trait for Bundles and MultiData types

  #1898·cyndquill opened Apr 7, 2026·2 tasks done·

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• Add support for automated Vivado IP TCL generation and simulation integration

  #1859·skylayer opened Dec 19, 2025Contributor·3 tasks done·

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• feat(sv interface): sv interface can be set to blackbox. add header comment when oneFilePerComponent

  #1829·yportne13 opened Oct 23, 2025Contributor·2 tasks·

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• Implement readResponseDelay in AxiMemorySim

  #1820·louiecaulfield opened Oct 1, 2025Contributor·

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• Add RoundType.NONE

  #1798·thajohns opened Sep 9, 2025·2 tasks·

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• Switch emit rework

  #1724·Dolu1990 opened May 5, 2025Member·

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• Change AFix division

  #1722·thajohns opened May 2, 2025·1 of 2 tasks·

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  4