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doc/gen: document the initialization with cpu: None. - #469
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With cpu: None, init_sequence() only sends the JEDEC commands, CSV addresses need a shift for wb_ctrl_adr, and the user ports stay blocked until ddrctrl_init_done is written. These regularly trip integrators (litedram #281, #315, #327). Describe the addresses, the sequence and this register. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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With
cpu: None, three things regularly trip integrators of the standalone core (#281, #315, #327):csr.csvgives byte addresses whilewb_ctrl_adris a word address.init_sequence()only sends the JEDEC commands, without the rest ofsdram_init().block_until_ready(the default), the user ports stay blocked untilddrctrl_init_doneis written, andinit_sequence()does not write it.This adds an "Initialization with
cpu: None" section todoc/gen.md.Documentation only. The sequence was checked against
sdram_init()inliblitedram. Theddrctrl_init_donebehaviour was checked in Verilator on a--simcore built from the #281 YAML: noackbefore the write, then 256 writes and 256 reads acked with correct data. No hardware.Written by Claude Code (AI agent), supervised by Florent Kermarrec.
🤖 Generated with Claude Code