[enjoy-digital]

Closes #306. Refs #185, #406.

Per speed grade timings (first commit)

• _SpeedgradeTimings accepts optional tCCD, tRRD, cl and cwl. tCCD/tRRD override the technology timings when set, and SDRAMModule.get_cl_cwl() returns the speed grade's CL/CWL.
• litedram_gen gets sdram_module_speedgrade (previously ignored), cl and cwl. CL/CWL come from the YAML, then the speed grade, else the PHY defaults. --sim cores do not use cl/cwl.
• An unknown sdram_module_speedgrade now raises a KeyError, where the key used to be ignored.

DDR4 tCCD (second commit)

• Hand-written DDR4 modules used tCCD=(4, None), so with sys_clk above 200 MHz at 1:4, consecutive CAS commands to a bank group were closer than tCCD_L.
• They now use tCCD_L from the Micron 8Gb DDR4 datasheet (Rev. L, Tables 161/162): 5 ns from DDR4-2400, and 5.355 ns for the two DDR4-2133 modules. Its minimum is 4nCK: "Although JEDEC specifies the larger of 5nCK or Xns, Micron's DRAM supports the larger of 4nCK or Xns."
• tCCD is now computed without the 3/4 sys_clk phase margin. That margin would give tCCD=2 at every usual clock and halve sequential throughput. It is not needed since consecutive CAS commands of the same type are on the same DFI phase.

Effect on tCCD (all modules, 10 clocks from 25 to 400 MHz, no other timing changes)

Modules	Change
DDR2, DDR3, SDR, LPDDR	None
Hand-written DDR4	None up to 156.25 MHz. 1 to 2 from 300 MHz, also at 200 MHz for the two 2133 modules, 1 to 3 at 400 MHz for those two
HMA82GR7DJR4N, HMA84GR7DJR4N, M393A2K40DB3, M393A4K40DB3	2 to 1 up to 200 MHz, 3 to 2 from 300 MHz

The four RDIMM modules, and modules built from SPD data, get more sequential throughput at usual clocks. That is the change most worth reviewing, since it relaxes real designs.

Known limits, not changed here

• tCCD_L depends on the operating rate: 6.25 ns at DDR4-1600. A module's value is for its speed grade's maximum rate, so a 5 ns module run at 200 MHz sys_clk (1600 MT/s at 1:4) gets 5 ns. This is above the 1250 MT/s component-mode limit, so it does not apply to USDDRPHY/USPDDRPHY today.
• JEDEC gives a 5nCK minimum. The 4nCK value comes from Micron's datasheet, and I did not check other vendors' parts.
• init.py still programs MR6 with format_mr6(4) # FIXME: tCCD. phy: add experimental UltraScale native DDR4 support #406 changes that line, so I left it to avoid a conflict.
• phy: add experimental UltraScale native DDR4 support #406 does not touch modules.py, and its tCCD == 2 check should now be met by these modules at 300 MHz and above. I did not run phy: add experimental UltraScale native DDR4 support #406 on this branch.

Tested

• test_modules, test_timing, test_controller_timing, test_gen, test_init, test_multiplexer, test_crossbar and test_controller pass.
• Generation of arty, ulx3s, kcu105, xcu1525 and a USP DDR4 core: with cl/cwl the init sequence has CL=11, and CL=9 without them.
• No hardware and no real-PHY throughput measurement.

Written by Claude Code (AI agent), supervised by Florent Kermarrec.

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