Issues

• [Feature request] adding FHDL module to synthesizable VHDL support

  m-labs/migen#311 · Filter by author ohault opened on May 30, 2025

• Invalid verilog representation

  m-labs/migen#308 · Filter by author ollie-etl opened on May 6, 2025

• VCD file may contain time stamps as floats

  m-labs/migen#306 · Filter by author oscargus opened on Apr 16, 2025
  1

• fsm.delayed_enter incompatible with vcd dump

  m-labs/migen#305 · Filter by author enurseitov opened on Apr 15, 2025
  1

• Support for negedge sensitivity list

  m-labs/migen#304 · Filter by author shantzis62 opened on Apr 12, 2025

• assignment of combinatorial values with delayed assignment gives incorrect results when referencing same signal

  m-labs/migen#303 · Filter by author jwise opened on Mar 11, 2025
  3

• Support for python 3.13

  m-labs/migen#297 · Filter by author jasonbridges opened on Dec 2, 2024

• Async FIFO Output is Broken when FIFO Depth is Set to 2

  m-labs/migen#296 · Filter by author linuswck opened on Nov 15, 2024

• else branch elided in generated Verilog

  m-labs/migen#274 · Filter by author McSherry opened on Jun 22, 2023
  3

• Better FMC support

  m-labs/migen#269 · Filter by author kaolpr opened on Nov 25, 2022
  1

• [Sim] Error with fsm delayed_enter method

  m-labs/migen#267 · Filter by author kamejoko80 opened on Oct 7, 2022

• move the conditional part of toolchain.build(run=True/False) to a separate method

  m-labs/migen#258 · Filter by author lneuhaus opened on Feb 22, 2022
  1

• Incorrect simulation of Cat()

  m-labs/migen#256 · Filter by author enurseitov opened on Feb 9, 2022
  3

• Signal Names of FSM

  m-labs/migen#247 · Filter by author navaneeth-cirel opened on Aug 26, 2021

• TSTriple() usage

  m-labs/migen#246 · Filter by author jimmymagemtek opened on Aug 20, 2021
  1

• Cycle accurate simulation

  m-labs/migen#238 · Filter by author navaneeth-cirel opened on May 21, 2021
  2

• Migen - Cat() simulation not matching verilog when Cat_object is sliced

  m-labs/migen#228 · Filter by author scted opened on Dec 6, 2020
  8

• python dependency wheel missing

  m-labs/migen#218 · Filter by author philipaxer opened on Sep 8, 2020

• Problem with copy_sources(self, build_dir, subdir="imports")

  m-labs/migen#207 · Filter by author andres-emb opened on Apr 5, 2020
  7

• Add more comments to examples

  m-labs/migen#197 · Filter by author TG-Techie opened on Dec 15, 2019
  1

• [migen][sim] How to import verilog source into migen design file ?

  question
  m-labs/migen#188 · Filter by author henrydang80 opened on Jul 8, 2019
  1

• .part() is converted to Verilog that can evaluate to 'x

  bugfixed-in-nmigen
  m-labs/migen#168 · Filter by author whitequark opened on Dec 16, 2018
  1

• << seems buggy

  bugfixed-in-nmigen
  m-labs/migen#165 · Filter by author whitequark opened on Nov 22, 2018
  2

• Finalization is order-dependent, leading to footguns

  bugfixed-in-nmigen
  m-labs/migen#158 · Filter by author whitequark opened on Nov 10, 2018
  1

• Negative initialization produces incorrect verilog

  bugfixed-in-nmigen
  m-labs/migen#142 · Filter by author JohnSully opened on Oct 9, 2018
  8