Issues

• pip install of tag 0.12 fails

  m-labs/misoc#146 · Filter by author ghost opened on Nov 9, 2023
  5

• register_rom weirdness

  m-labs/misoc#96 · Filter by author keesj opened on Jan 29, 2019
  2

• CSRStorage with write_from_dev=True seems broken in simulation

  m-labs/misoc#95 · Filter by author mithro opened on Dec 11, 2018
  4

• software not rebuilt after gateware change

  m-labs/misoc#91 · Filter by author danielkucera opened on Jul 29, 2018

• Standard 1 bit SPI mode for spi_flash not available?

  m-labs/misoc#87 · Filter by author danielkucera opened on Jul 28, 2018
  2

• Binutils compilation

  m-labs/misoc#83 · Filter by author danielkucera opened on Jun 21, 2018

• kasli/spi_flash: investigate and implement quad i/o read

  improvement
  m-labs/misoc#74 · Filter by author jordens opened on Jan 5, 2018

• clean up memory regions, names, offsets

  improvement
  m-labs/misoc#73 · Filter by author jordens opened on Jan 3, 2018

• liteeth: remove MII clock output

  m-labs/misoc#72 · Filter by author sbourdeauducq opened on Dec 18, 2017
  

• fix liteeth error counter atomicity problem

  m-labs/misoc#69 · Filter by author sbourdeauducq opened on Dec 15, 2017
  2

  

• cross check SPI core w.r.t. Vivado changes

  m-labs/misoc#58 · Filter by author jordens opened on Oct 25, 2017

• merge a7ddrphy and k7ddrphy

  m-labs/misoc#57 · Filter by author sbourdeauducq opened on Oct 11, 2017
  5

• support 4 byte spi flash addressing

  m-labs/misoc#53 · Filter by author jordens opened on Aug 8, 2017
  1

• remove FlipFlop

  m-labs/misoc#51 · Filter by author sbourdeauducq opened on Jul 13, 2017

• setup.py fails on Ubuntu 16.04

  m-labs/misoc#50 · Filter by author John-K opened on Mar 21, 2017
  2

• Create a "spi settings" type thing (in same vein as the SDRAM settings)

  m-labs/misoc#48 · Filter by author mithro opened on Dec 20, 2016
  2

  

• Framebuffer core depends on migen.actorlib

  m-labs/misoc#46 · Filter by author mithro opened on Dec 15, 2016
  1

  

• remove converter reset from liteeth mii.py

  m-labs/misoc#44 · Filter by author sbourdeauducq opened on Nov 16, 2016
  

• define stream behavior when stb=0 and eop=1

  m-labs/misoc#43 · Filter by author sbourdeauducq opened on Nov 16, 2016
  2

  

• Wishbone SRAM: support memories larger than the bus width

  m-labs/misoc#42 · Filter by author sbourdeauducq opened on Nov 13, 2016

• move liteeth FullMemoryWE transform to migen.build

  m-labs/misoc#41 · Filter by author sbourdeauducq opened on Nov 12, 2016

• minicon: avoid oversized address signal

  m-labs/misoc#40 · Filter by author sbourdeauducq opened on Oct 5, 2016

• BIOS should use '\r\n' line endings

  m-labs/misoc#38 · Filter by author mithro opened on Apr 18, 2016

• CSR should have read and write swapped to master perspective

  m-labs/misoc#33 · Filter by author sbourdeauducq opened on Mar 2, 2016 · 2.0

• python setup.py install works without git submodule being initialized

  m-labs/misoc#26 · Filter by author mithro opened on Dec 24, 2015
  5