Skip to content

[multi-vector] Detect L1/L2 cache sizes for matrix kernels - #1134

Open
Wei Wu (wuw92) wants to merge 4 commits into
mainfrom
users/wuw92/cache-size-detection
Open

Wei Wu (wuw92) wants to merge 4 commits into
mainfrom
users/wuw92/cache-size-detection

Conversation

@wuw92

@wuw92 Wei Wu (wuw92) commented Jun 5, 2026

Copy link
Copy Markdown
Contributor
  • Does this PR have a descriptive title that could go in our release notes?
  • Does this PR add any new dependencies?
  • Does this PR modify any existing APIs?
  • Is the change to the API backwards compatible?
  • Should this result in any changes to our documentation, either updating existing docs or adding new ones?

Adds target-specific dependencies on raw-cpuid and libc. No public API signatures change. Internal cache-budget documentation is updated.

Reference Issues/PRs

Builds on the matrix-kernel design introduced in #1368.

What does this implement/fix? Briefly explain your changes.

matrix_kernels::Cache::detect() still derives its budgets from hardcoded cache-size estimates of 48 KB L1d and 1.25 MB L2. This change replaces those estimates with runtime-detected sizes, memoized once per process.

Detection is architecture-first: CPUID where available, OS APIs otherwise.

Arch / OS Mechanism
x86_64 (Windows, Linux, macOS) CPUID via raw-cpuid
aarch64 Linux sysfs
aarch64 macOS sysctl hw.perflevel0.*, with L2 divided by cpusperl2
Unsupported targets or unavailable probes 48 KB L1d / 1.25 MB L2 fallback

@wuw92
Wei Wu (wuw92) requested review from a team and Copilot June 5, 2026 03:54
@wuw92 Wei Wu (wuw92) changed the title [diskann-quantization] Detect L1/L2 cache sizes for tile budget [multi-vector] Detect L1/L2 cache sizes for tile budget Jun 5, 2026

Copilot AI left a comment

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Pull request overview

This PR updates the multi-vector distance tiling planner in diskann-quantization to derive its tile budgets from runtime-detected L1d/L2 cache sizes (with per-arch fallbacks), replacing the prior hardcoded Skylake-X assumptions.

Changes:

  • Added a memoized cache-size probe (L1d, L2) with x86_64 CPUID detection and aarch64 Linux/macOS OS-specific probes, plus a conservative fallback.
  • Updated TileBudget::default() to use detected cache sizes when computing L1/L2-derived budgets for tile planning.
  • Introduced target-specific dependencies (raw-cpuid on x86_64; libc on aarch64 macOS) to support probing.

Reviewed changes

Copilot reviewed 7 out of 8 changed files in this pull request and generated 2 comments.

Show a summary per file
File Description
diskann-quantization/src/multi_vector/distance/mod.rs Wires in the new cache submodule.
diskann-quantization/src/multi_vector/distance/kernels/mod.rs Switches TileBudget::default() to runtime-detected cache sizes.
diskann-quantization/src/multi_vector/distance/cache/mod.rs Adds memoized cache probing API and basic plausibility/memoization tests.
diskann-quantization/src/multi_vector/distance/cache/cpuid.rs Implements x86_64 cache detection using raw-cpuid.
diskann-quantization/src/multi_vector/distance/cache/linux.rs Implements aarch64 Linux detection via sysfs cache entries.
diskann-quantization/src/multi_vector/distance/cache/macos.rs Implements aarch64 macOS detection via sysctl hw.perflevel0.*.
diskann-quantization/Cargo.toml Adds target-specific dependencies for the detection paths.
Cargo.lock Records the new dependency resolutions.

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

Comment thread diskann-quantization/src/multi_vector/distance/cache/cpuid.rs Outdated
Comment thread diskann-quantization/src/matrix_kernels/cache/linux.rs
@codecov-commenter

Codecov Comments Bot (codecov-commenter) commented Jun 5, 2026

Copy link
Copy Markdown

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 91.53%. Comparing base (765c794) to head (92b822b).

Additional details and impacted files

Impacted file tree graph

@@            Coverage Diff             @@
##             main    #1134      +/-   ##
==========================================
+ Coverage   91.52%   91.53%   +0.01%     
==========================================
  Files         526      528       +2     
  Lines      103087   103140      +53     
==========================================
+ Hits        94351    94414      +63     
+ Misses       8736     8726      -10     
Flag Coverage Δ
miri 91.53% <100.00%> (+0.01%) ⬆️
unittests 91.28% <100.00%> (+0.01%) ⬆️

Flags with carried forward coverage won't be shown. Click here to find out more.

Files with missing lines Coverage Δ
...ann-quantization/src/matrix_kernels/cache/cpuid.rs 100.00% <100.00%> (ø)
...skann-quantization/src/matrix_kernels/cache/mod.rs 100.00% <100.00%> (ø)
diskann-quantization/src/matrix_kernels/mod.rs 100.00% <100.00%> (ø)

... and 8 files with indirect coverage changes

🚀 New features to boost your workflow:
  • ❄️ Test Analytics: Detect flaky tests, report on failures, and find test suite problems.

@wuw92
Wei Wu (wuw92) force-pushed the users/wuw92/cache-size-detection branch from c909e67 to 1a9a5c2 Compare September 17, 2026 03:13
@wuw92 Wei Wu (wuw92) changed the title [multi-vector] Detect L1/L2 cache sizes for tile budget [multi-vector] Detect L1/L2 cache sizes for matrix kernels Sep 17, 2026
Wei Wu (wuw92) and others added 4 commits September 17, 2026 15:46
…tile budget

Wires runtime L1d/L2 detection into TileBudget::default() so the
multi-vector tile planner sizes A/B tiles against the host's actual
cache geometry instead of hardcoded Skylake-X estimates (1.25 MB L2,
48 KB L1d from PR #863).

Detection lives in diskann-quantization, alongside the existing
ISA-capability probe in isa.rs. Cache size is fundamentally a CPU/arch
property: the OS-API is a discovery mechanism, not the concept being
captured. Putting the module here mirrors the existing
diskann-wide / diskann-vector / diskann-quantization stack, which
handles all arch dispatch internally without depending on
diskann-platform.

Detection strategy follows what gemm-common / faer / OpenBLAS do:
CPUID where available, OS API where required.

- x86_64 (any OS):     CPUID via the `raw-cpuid` crate (one path)
- aarch64 Linux:       sysfs (/sys/devices/system/cpu/cpu0/cache/...)
- aarch64 macOS:       sysctl (hw.perflevel0.*, P-core L2 / cpusperl2)
- Anything else:       CacheInfo::FALLBACK (32 KB L1d, 256 KB L2)

On Apple Silicon the per-cluster L2 is divided by cpusperl2 to give a
per-core budget. Windows-on-ARM falls back to the conservative
defaults: CI doesn't cover that target and DiskANN production doesn't
deploy there; dropping it removes a Win32 codepath and lets the crate
avoid pulling windows-sys.

Equality between CPUID and Win32 GetLogicalProcessorInformationEx was
verified on Windows x86_64 (32 KB L1d / 512 KB L2 on the test host)
during development. Final commit removes the side-by-side test along
with the temporary dependency on diskann-platform.

Closes #1062.
- cpuid.rs: reword the module doc so the CPUID 0x4 / 0x8000001D leaf
  selection is attributed to raw-cpuid's cache-parameter enumeration.
  The vendor dispatch is internal to the crate, not visible at our call
  site, which the original wording obscured.
- linux.rs: parse_size uses checked_mul for the K/M/G suffixes so an
  oversized sysfs value returns None instead of silently wrapping in
  release builds, where overflow checks are off. Add a regression test.
Move platform probes under matrix_kernels and feed Cache::detect with memoized L1d/L2 sizes. Preserve the new drivers' budget fractions and nonzero invariants, with regression coverage for budget scaling and blocking parameters.

Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>
Keep probe results optional and select legacy cache estimates in Cache::detect before applying the shared budget fractions. Clarify budget documentation and remove hardware-dependent and redundant tests.

Co-authored-by: Copilot App <223556219+Copilot@users.noreply.github.com>
@wuw92
Wei Wu (wuw92) force-pushed the users/wuw92/cache-size-detection branch from 1a9a5c2 to 92b822b Compare September 17, 2026 07:49
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

Add support for reading L1/L2 cache sizes for different platforms(Windows, Linux, MacOS) for our efficient cache aware multi-vector distance functions.

3 participants