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QSF writes the Quartus settings file and SDC the timing constraints, from the same board and design declarations as LPF; Quartus writes a whole workspace with build.sh and a Makefile whose load and flash targets use openFPGALoader, since Quartus's own programmer runs only where Quartus does. The device prefix picks the vendor, and each emitter refuses the other vendor's part. A board-wide I/O standard also becomes the device default, because Quartus otherwise supplies the banks no port lands in at 2.5 V and the configuration pins end up across two voltages. The app writes .qsf and .sdc beside the Verilog for such a board and accepts --emit Quartus. The yosys depth estimate knows the Intel families. Checked by compiling a blinky for the MAX 10 10M08S evaluation kit in Quartus Prime 25.1: no errors, no I/O warnings, timing closed at 50 MHz. Loading on the board awaits the cable.
mchitre
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+ Coverage 88.42% 88.63% +0.21%
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The board binding, constraint file and Diamond workspace tests were spread over runtests.jl, soc.jl and timing.jl, each beside the design it used, while the Quartus side arrived in one file. Both tool chains now have a file of their own, named for the tool as the emitters are. The tests move unchanged, except that the check that the rate units are not exported no longer depends on running before `using QuartzHDL.Units`.
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Summary
QSF(board)writes the Quartus settings file andSDC(board)the timing constraints, from the same declarations asLPF.Quartus(board)writes a whole workspace withbuild.shand a Makefile whoseloadandflashtargets use openFPGALoader..qsfand.sdcbeside the Verilog for such a board and accepts--emit Quartus. The yosys depth estimate knows the Intel families.docs/.Checks
Pkg.test()green with iverilog, including newtest/quartus.jland command-line checks.