Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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Updated
Feb 9, 2022 - SystemVerilog
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
ZCU102 two IMX274 camera design.
AXI 1G Ethernet ref designs for the Opsero Ethernet FMC Max (OP080)
Zynq Ultrascale+ Core Board
Collection of FPGA modules for video capture and processing.
Vivado board part for the RIGUKE RK-XCKU5P-F V1.2 (XCKU5P-FFVB676-2-I): board definition, pin map, IP presets, and the XDMA GTY_Quad_224 placement fix for PCIe Gen3 x4.
FPGA SDR receiver on Xilinx KU5P + AD9361: FM broadcast radio, airband AM (118-137 MHz), open JTAG-to-AXI bridge (FT2232H MPSSE, no Vivado at runtime), Flutter Windows app. FPGA 软件无线电收音机
i2c-xiic driver with added support for master_xfer_atomic()
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