verihogg
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Surelog
Surelog PublicForked from chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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sv-tests
sv-tests PublicForked from chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
SystemVerilog
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scr1
scr1 PublicForked from syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog
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sv-tests-results
sv-tests-results PublicForked from chipsalliance/sv-tests-results
Output of the sv-tests runs.
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- verihogg-format Public
- sv-tests Public Forked from chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
- verihogg-lint Public
- scr1 Public Forked from syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
- Surelog Public Forked from chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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