Addressing Modes v1

Addressing Modes

This is Version 1 of the CPU design, which is now out-of-date.

Supported Modes

See the Instructions wiki page to see which addressing modes are supported by each CPU instruction.

Mode	Abbreviation	Description
Register	REG	Operand is a CPU register encoded in the opcode.
Immediate	IMM	Operand is a literal value included as second byte of the instruction; denoted with #
Direct	DIR	LSB of address of operand is the second byte of the instruction; denoted with ( and )
Indirect	IND	Operand is implicit in the instruction
Bit	BIT	Manipulate a specific bit within a register

Unsupported Modes

Register Indirect and/or Indexed addressing modes may be supported at a future time, either by the Assembler or the CPU directly.

History

Date	Changes
02-Oct-2025	Created