Registers

Registers

This is Version 2 of the CPU design.

List

AA	Register A	Accumulator register, data path to most other registers
AB	Register B	Connected to ALU as second operand
AC	Register C	Use as a counter and temporary storage; not connected to ALU
FL	Flags	SIGN (S), ZERO (Z), CARRY (C) , OVERFLOW (V)
SH	Stack Pointer MSB
SL	Stack Pointer LSB
MH	Memory Pointer MSB	MSB of memory location use by LOAD and STOR instructions
ML	Memory Pointer LSB	LSB of memory location use by LOAD and STOR instructions
JH	Jump Address MSB	MSB of jump-to address for the for JUMP and JPxx instructions
JL	Jump Address LSB	LSB of jump-to address; only used by the register mode version of JUMP
PC	Program Counter	This is a 16-bit value, indirectly accessible through jump instructions
IR	Instruction	Last opcode fetched from memory; not accessible to user

SH and SL are the MSB and LSB of the 16-bit SP register.
MH and ML are the MSB and LSB of the 16-bit MR register.
JH and JL are the MSB and LSB of the 16-bit JR register.

Hardware Implementation

Register	Qty	Part	Description
AA	1	74HC273	Octal DFF with clear
AB	2	74HC161	4-bit presettable counter
AC	2	74HC161	4-bit presettable counter
FL	2	74HC109	Dual JKFF with async clear and preset
SH	2	74HC193	4-bit presettable up/down counter with clear
SL	2	74HC193	4-bit presettable up/down counter with clear
MH	2	74HC161	4-bit presettable counter
ML	2	74HC161	4-bit presettable counter
JH	1	74HC273	Octal DFF with clear
JL	1	74HC273	Octal DFF with clear
PC	4	74HC161	4-bit presettable counter

History

Date	Changes
15-Oct-2025	Created - Design Version 2
06-Dec-2025	Add register AC (see 06-Dec-2025 blog entry), 74HC logic implementation