Changes From Version 1

Design Changes From Version 1

After working through the CPU design to support the two byte opcodes list, I realized that I need to use 8-bit instructions, not 16-bit. Most of the instructions don't use the second byte, wasting memory space and clock cycles. Also, since 2 clock cycles were needed to fetch the instruction, then the execution phase also needed to take 2 clock cycles.

Other RISC CPUs use the memory data path size as the instruction length, so that the entire instruction can be read in one memory access. This works well for 16, 32 and 64-bit CPUs, because even after encoding the instructions, there are still many bits left over to encode an immediate value.

So what I really need to do is fit my instructions into 8-bit opcodes. Other alternatives would be to switch to a Harvard architecture with a 16-bit wide ROM for instructions, and a separate 8-bit RAM for data. That is how Gigatron does it, but this feels like breaking a key design goal to make an 8-bit processor (8-bit data bus, 16-bit address bus).

In order to fit all instructions into 8 bits, then only 4 bits are available for an operand. So it will take 2 instructions load an 8 bit immediate value, or 4 instructions to load a 16 bit immediate (e.g., for a jump). This can be masked from the user by having the assembler support full 8-bit or 16-bit immediates.

So, this new design and instruction set makes the following changes to version 1 of the design:

• All opcodes are 8-bits, supporting a 4-bit immediate operand for a small set of instructions
  • Added several instructions to load commonly-used 8-bit values ($00, $01, $FF) into certain registers with a single instruction
• Rename AC to AA (accumulator A) and create new AB (accumulator B) -- AB replaces OR, plus it is slightly more usable as a general-purpose register
• Create a new register ML, which combined with MH create a 16-bit register, MR, used as the memory location for LOAD (MR) and STOR (MR) instructions
• The rotate instructions RRTC and RLTC don't quite work for the purpose I was considering (multi-byte multiply and divide). They will be replaced by:
  • SRAC (shift right arithmetic through C), for signed integers
  • SRLC (shift right logical through C), for unsigned integers
  • SLLC (shift left logical through C), for either signed or unsigned
  • The other rotate instructions are removed
• Add instructions INCA, INCB, DECA, DECB, DECM
• Flag bits are in the upper nibble of FL so that S flag is bit 7 (same as the sign bit in a byte)
• Some other opcode mnemonics are renamed for clarity

History

Date	Changes
15-Oct-2025	Created - Design Version 2